1. Field of the Invention
The present invention relates to a method of forming a silicon oxide layer of a semiconductor device and a method of forming a wiring having the same, and more particularly to a method of forming a silicon oxide layer capable of insulating between patterns without oxidizing other layers and a method of forming a wiring having the silicon oxide layer.
2. Description of the Related Art
As semiconductor devices are highly integrated with high processing speed, it is required to form fine patterns. In this regard, widths of patterns as well as space between patterns are remarkably reduced. Accordingly, it becomes very difficult to fill a silicon oxide layer into a narrow space between patterns for insulating between patterns.
A PE-CVD process, which is generally used for forming layers of a semiconductor device, cannot completely insulate patterns having a narrow space therebetween. For this reason, a method for forming the silicon oxide layer by using an SOG layer or a BPSG layer having a superior gap fill characteristic is suggested.
FIGS. 1A to 1D are sectional views showing a conventional method of forming a silicon oxide layer for insulating fine patterns from each other.
Referring to FIG. 1A, an insulating layer 14 including a plurality of first conductive patterns 12 therein is formed on a semiconductor substrate 10. Particularly, after forming a conductive layer on the semiconductor substrate 10 or the semiconductor substrate 10 having a predetermined layer formed thereon, the conductive layer is patterned so as to form the plurality of first conductive patterns 12. Then, the insulating layer 14 is formed to bury the first conductive patterns 12.
Thereafter, second conductive patterns 16 are formed on the insulating layer 14. At this time, the second conductive patterns 16 are located at positions above the corresponding portions between the first conductive patterns 12. The second conductive pattern 16 is a composite pattern including a metal layer pattern 16a and a nitride layer pattern 16b that is sequentially formed on the metal layer pattern 16a. The nitride layer pattern 16b is formed by patterning a nitride layer after forming a nitride layer using a PE-CVD process.
Referring to FIG. 1B, a nitride layer spacer 18 is formed at sidewalls of the second conductive pattern 16. The nitride layer spacer 18 is used for forming a self-aligned contact hole through subsequent processes. The self-aligned contact hole is conductively communicated with lower first conductive patterns 12.
In detail, the nitride layer is sequentially formed on the sidewalls and upper portions of the second conductive layer patterns 16 and an upper surface of the insulating layer 14. The nitride layer is formed through an LP-CVD process. Then, the nitride layer is anisotropically etched such that the nitride layer remains only on the sidewalls of the second conductive patterns 16, thereby forming the nitride layer spacer 18.
Referring to FIG. 1C, a reflowable oxide layer 20 is formed so as to bury spaces between second conductive patterns 16 formed with the nitride layer spacer 18 and the second conductive patterns 16. The reflowable oxide layer 20 is formed as an SOG layer or a BPSG layer.
Referring to FIG. 1D, a silicon oxide layer 22 is formed by heat-treating the reflowable oxide layer 20.
That is, if the SOG layer is heat-treated in an oxygen atmosphere, Sixe2x80x94N or Sixe2x80x94H bond is replaced with Sixe2x80x94O bond so the silicon oxide layer 22 is formed. In addition, the BPSG layer is formed as a planar layer 38 through a reflow process, in which the BPSG layer is heat-treated in the oxygen atmosphere, while burying the second conductive patterns 16 and the spaces between second conductive patterns 16.
At this time, oxygen used for heat-treating the SOG layer or the BPSG layer penetrates into the second conductive patterns 16. That is, oxygen penetrates into a pin hole of a nitride layer pattern 16b of the second conductive layer pattern 16 and an interfacial surface of the nitride layer spacer 18, so the metal layer pattern 16a of the second conductive layer pattern 16 is oxidized.
Particularly, since the nitride layer pattern 16b of the second conductive layer pattern 16 is formed through the PE-CVD process, the nitride layer pattern 16b is roughly formed so the pin holes may be formed in the nitride layer pattern 16b, so that the metal layer pattern 16 is frequently oxidized.
When the metal layer pattern 16a is oxidized, a volume of the metal layer pattern is enlarged, so that the metal layer pattern is upwardly lifted caused by the enlarged volume thereof which is called xe2x80x9ca metal lifting failurexe2x80x9d. In addition, the lifting of the metal layer pattern causes a crack to the silicon oxide layer. If the second conductive layer pattern is formed in a conductive line type, the conductive line can be disconnected caused by the lifting of the meal layer pattern, thereby causing a failure of the semiconductor device.
U.S. Pat. No. 5,879,986 discloses a method of forming a silicon oxide layer for insulating between fine patterns and of forming a wiring. According to the above patent, a nitride layer is formed on a conductive layer pattern through a PE-CVD process. Then, an oxide layer is formed while burying a space between the conductive layer and an insulating layer. The oxide layer is formed through the PE-CVD process. However, if a fine space is formed between conductive layer patterns, forming the oxide layer insulating between the conductive layer patterns via the PE-CVD is difficult.
Recently, a method for forming an insulating layer through an HDP (high density plasma) CVD process is suggested for forming the insulating layer between fine conductive layer patterns. However, the HDP CVD process also has a limitation for forming the insulating layer between the fine conductive layer patterns.
The present invention has been made to solve the above problems of the prior art, therefore, it is a first object of the present invention to provide a method for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive layer patterns without causing a process failure.
The second object of the present invention is to provide a method for forming a wiring of a semiconductor device having a silicon oxide layer capable of insulating between fine conductive layer patterns without causing a failure.
In accordance with an aspect of the present invention, a method of forming an insulating layer in a semiconductor device is provided. In accordance with the method, a plurality of conductive patterns are formed on a semiconductor substrate. An anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate for preventing an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating reflowable oxidizing materials on the conductive patterns formed with the anti-oxidation layer while burying the conductive patterns. A silicon oxide layer is formed by thermally treating the reflowable oxide layer.
In accordance with a second aspect of the present invention, a method of forming a wiring in a semiconductor device is provided. In accordance with the method, an insulating layer including a plurality of first conductive patterns therein is formed on a semiconductor substrate. Second conductive patterns are formed on portions of the insulating layer corresponding to spaces formed between first conductive patterns. An anti-oxidation layer is sequentially formed on upper surfaces of the second conductive patterns and the insulating layer for preventing an oxidant from penetrating into the second conductive patterns and the insulating layer. A reflowable oxide layer is formed by coating a reflowable oxide on the anti-oxidation layer while burying the second conductive patterns. A silicon oxide layer is formed by thermally treating the reflowable oxide layer. A preliminary contact hole is formed for exposing the anti-oxidation layer formed on the insulating layer by anisotropically etching a predetermined portion of the silicon oxide layer. The anti-oxidation layer exposed to the upper surface of the insulating layer and the insulating layer are anisotropically etched, in sequence, thereby forming a contact hole for exposing an upper surface of the first conductive patterns. A conductive material is filled in the contact hole, thereby completing a wiring of a semiconductor device.
In accordance with another aspect of the present invention, a method of forming a wiring in a semiconductor device is provided. In accordance with the method, an insulating layer including a plurality of first conductive patterns therein is formed on a semiconductor substrate. Second conductive patterns are formed on portions of the insulating layer corresponding to spaces formed between first conductive patterns. A nitride layer spacer is formed at sidewalls of the second conductive patterns. A first preliminary contact hole is formed for exposing an upper surface of the first conductive patterns by performing an anisotropic etching process using the nitride layer spacer as an etching mask. An anti-oxidation layer is sequentially formed on an upper surface of the second conductive pattern, an upper surface of the insulating layer, and a sidewall and a bottom surface of the first preliminary contact hole, for preventing an oxidant from penetrating thereinto. A reflowable oxide layer is formed by coating a reflowable oxide on the anti-oxidation layer while burying the first preliminary contact hole. A silicon oxide layer is formed by thermally treating the reflowable oxide layer. A second preliminary contact hole is formed by anisotropically etching a predetermined portion of the silicon oxide layer, thereby exposing the anti-oxidation layer formed on the bottom surface of the first preliminary contact hole. The exposed anti-oxidation layer is etched so as to form a contact hole for exposing the upper surface of the first conductive patterns. A conductive material is filled in the contact hole, thereby completing a wiring of a semiconductor device.
By forming the anti-oxidation layer, the conductive patterns can be prevented from being oxidized when the silicon oxide layer is formed. In addition, since the silicon oxide layer is formed by thermally treating the reflowable oxide layer, the silicon oxide layer has a superior gap-filling characteristic.